1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a semiconductor chip is bonded to a metal cap.
2. Description of Related Art
In order to reduce a size of a semiconductor device through which a larger current flows, such as a power metal-oxide semiconductor field-effect transistor (MOSFET), there is developed a chip size package (CSP) in which a semiconductor chip is mounted to a metal cap having integrally-formed external connection terminals. FIG. 1 shows a semiconductor device 100 shown in FIG. 8 of JP 2004-040008 A (equivalent to United States Patent Application Publication No. US 2004/0021216 A1 (hereinafter referred to as “Hosoya”)). A gate electrode 5, a source electrode 6, and surface electrodes 15 each electrically connected thereto are formed on a principal surface of a semiconductor chip 2. The surface electrodes 15 are electrically connected to, for example, a printed circuit board (not shown). A drain electrode 4 is formed on a rear surface of the semiconductor chip 2 and bonded to a metal cap 20 by a bonding material (not shown). Both side portions of the metal cap 20 are bent. External connection terminals 13 for electrically connecting the drain electrode 4 to, for example, the printed circuit board (not shown) are formed in the bent side portions.
In the semiconductor device 100, the bent side portions of the metal cap 20 are partially cut away to form the external connection terminals 13. The cutaway is made such that an area of parts of the external connection terminals 13 of the metal cap 20, which are connected to the printed circuit board or the like, is substantially equal to an area of parts of the plurality of surface electrodes 15 of the semiconductor chip 2, which are connected to the printed circuit board or the like. Therefore, a heat capacity of the surface electrode 15 side becomes equal to a heat capacity of the external connection terminal 13 side, so an excellent connection structure can be obtained.
The semiconductor device 100 is extremely effective to extract a larger current from the semiconductor chip 2 and to release heat from the semiconductor chip 2. In the case of the semiconductor device 100, a solder material is used as a bonding material for bonding the semiconductor chip 2 to the metal cap 20. The metal cap 20 is made of a material containing copper (Cu) as a main ingredient and has a linear expansion coefficient which is four or five times higher than a linear expansion coefficient of the semiconductor chip 2 made of silicon (Si). Therefore, thermal stress is produced in a bonding region between the metal cap 20 and the semiconductor chip 2 because of a temperature difference repeatedly caused during a temperature cycle test or actual use. Thus, the inventor of the present invention has found that the solder material might be peeled off to increase an electrical resistance and a thermal resistance.
When members having different linear expansion coefficients are bonded to each other, in order to reduce thermal stress produced between the members, it may be necessary to lower elastic coefficients of the members or an elastic coefficient of the bonding material or to reduce a bonding area therebetween. In general, in order to absorb the thermal stress between the semiconductor chip and the metal cap, for example, a silicone resin which contains silver (Ag) fillers and has a low elastic coefficient may be used as the bonding material. However, in the case of the semiconductor device through which the larger current flows, such as the power MOSFET, it is necessary to lower the electrical resistance of the bonding material, and a volume resistivity of the Ag filler is two to ten times higher than a volume resistivity of the solder material, so the solder material is used in many cases. As a result, thermal stress is produced in an inner portion of the solder material, an interface between the solder material and the semiconductor chip, and an interface between the solder material and the metal cap, which causes peeling between the members.
FIG. 2A shows a semiconductor device 200 shown in FIG. 1 of JP 58-033860 A (equivalent to U.S. Pat. No. 4,415,025 (hereinafter referred to as “Horvath”)). In the semiconductor device 200 which is not the CSP, the semiconductor chips 2 are connected to a substrate 21 through the surface electrodes 15 formed on the principal surface thereof, and the rear surface of each of the semiconductor chips 2 is bonded to a finned cap 22 through a thermal bridge element 24 made of metal.
FIG. 2B is a plan view showing the thermal bridge element 24. The thermal bridge element 24 has slits 26 radially formed from the center and slits 28 formed from the circumference toward the center. The slits 26 and 28 provide flexibility to the thermal bridge element 24, so a load on each of the semiconductor chips 2 can be adjusted.
In the case of the semiconductor device 200, in order to bond each of the semiconductor chips 2 to the finned cap 22, the thermal bridge element 24 having flexibility is interposed therebetween, so thermal stress may be reduced. However, FIG. 5 of Horvath shows that, in order to release heat generated by the semiconductor chips 2 to the finned cap 22, it is desirable to narrow a gap between each of the semiconductor chips 2 and the finned cap 22 and to increase curvature radii R1 and R2 of the thermal bridge element 24. That is, it is difficult to reduce a size of the thermal bridge element 24, so the semiconductor device 200 cannot be reduced in size so as to be equal to the CSP such as the semiconductor device 100 of Hosoya. It is necessary to bond each of the semiconductor chips 2 to the thermal bridge element 24 by a low melting point metal 25 and to bond the thermal bridge element 24 to the finned cap 22 by a low melting point metal 27, thereby increasing a manufacturing cost.